1. Technical Field
The present invention relates to a semiconductor memory cell as well as to an associated production method and, in particular, to a semiconductor memory cell having a contact hole capacitor.
2. Background Information
Future semiconductor components will have a great demand for large, high-density memory zones. The overall take-up of the available chip surface by such embedded memory zones is now already about 50% of the total chip surface, and will increase further. High-density semiconductor memory cells are therefore necessary to keep the memory zone as small as possible and reduce the overall size of the semiconductor component, so that the production costs can also be reduced. For this reason, the semiconductor industry is following a trend away from conventional 6-transistor semiconductor memory cells to 1-transistor, 2-transistor and 3-transistor (1T, 2T, 3T) semiconductor memory cells, so that a high integration density, an improved yield and a lower so-called soft error sensitivity is obtained with reduced leakage currents.
In contrast to a 6-transistor semiconductor memory cell, however, 1-transistor, 2-transistor and 3-transistor semiconductor memory cells require a capacitance or capacitor for storing charges and a refresh of the stored charges at predetermined time intervals. Since the refresh rate of embedded 1T, 2T and 3T semiconductor memory cells can be much more than that of conventional dynamic random access memories (DRAMs), it is possible to use small storage capacitors.
FIGS. 1 to 3 show simplified equivalent circuit diagrams respectively for a 1-transistor, 2-transistor and 3-transistor semiconductor memory cell, BL denoting a bit line, WL denoting a word line and AT denoting a respective selection transistor, via which a storage capacitor C can be driven.
According to FIG. 2, inverted word lines WL/ and inverted bit lines BL/, which drive the storage capacitor C via a further selection transistor AT, are furthermore provided in the 2-transistor semiconductor memory cell.
According to FIG. 3, the storage capacitor C in the 3-transistor semiconductor memory cell is on the one hand written to via a write bit line BLW and a write word line WLW and an associated selection transistor AT and read out via a read word line WLR and a read bit line BLR and two further associated selection transistors AT. To produce such 1T, 2T, 3T semiconductor memory cells, for example, so-called embedded DRAM semiconductor memory cells are used.
FIG. 4 shows a simplified sectional view of such a 1-transistor semiconductor memory cell with a deep trench capacitor. According to FIG. 4 there is a deep trench for producing a deep trench capacitor DTC in a semiconductor substrate 10, a capacitor dielectric (CD) being formed on the trench surface and an electrically conductive filler layer, which together with the semiconductor substrate 10 as the other capacitor electrode produces the deep trench capacitor DTC, is formed as a capacitor counter electrode CE1 on the surface of the capacitor dielectric. Field-effect transistors with a source region S and a drain region D for establishing a channel in the semiconductor substrate 10 are conventionally used as selection transistors AT, a gate dielectric 60 being formed on the surface of the channel, and a control electrode or a gate G, which essentially produces a word line WL, being formed thereon. The source region S is connected for example via a source contact KS or a corresponding contact-via to a bit line BL which, for example, lies in a metallization plane. Similarly, the drain region D is connected for example via a first metallization plane M1, a drain contact KD and a capacitor contact KC to the deep trench capacitor DTC, or its capacitor counter electrode CE1.
Semiconductor circuits for establishing active areas AA, in particular for insulating the switching elements, for example the selection transistor AT, furthermore comprise so-called shallow trench isolations STI which, for example, have an insulating liner layer 20 and an insulation filler layer 30.
Although semiconductor memory cells with a very small space requirement can be produced with such DRAM semiconductor memory cells owing to the use of deep trench capacitors DTC, the costs are extraordinarily high in particular because of the production process for the deep trench capacitor DTC. Conventionally, 1T, 2T and 3T semiconductor memory cells are therefore currently produced with so-called MOS/MIM capacitors (MOS/MIM caps) which are substantially more cost-effective to produce.
FIG. 5 shows a simplified sectional view of a 1-transistor semiconductor memory cell with such an MOS capacitor MOSC, the same reference numerals denoting identical or corresponding elements as in FIG. 1 and repeated description being omitted below. According to FIG. 5, the storage capacitor is consequently produced by an MOS capacitor MOSC, the semiconductor substrate 10 or a doping region formed therein being used as a capacitor electrode CE2, on the surface of which a capacitor dielectric CD is formed with a capacitor counter-electrode CE1 being formed thereon for example as a polycrystalline semiconductor layer. The capacitor counter electrode CE1 is in turn electrically connected via a capacitor contact KC and a drain contact KD and a preferably first metallization plane M1 to the drain region D of the selection transistor AT. Although this can substantially reduce the costs, the area requirement for such a semiconductor memory cell is greatly increased since the MOS or MIM capacitor MOSC is essentially formed on the surface of the semiconductor substrate 10 and its capacitance is therefore directly proportional to the area occupancy of the available component surface.